Data processing and communicating system with high throughput peripheral component interconnect bus
US5958032A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 17, 1997 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Jul 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data communication system has a host bus connected to a central processing unit and a system memory, a peripheral component interconnect bus connected to a communication device equipped with a first state machine and a second state machine independently requesting a right to use the peripheral component interconnect bus and a bus bridge circuit connected between the host bus and the peripheral component interconnect bus and having a first-in-first-out memory for data read-out, and the bus first-in-first-out memory for data write-in and another bridge circuit assigns the right to use the peripheral component interconnect bus to the second state machine so as to transfer write-in data codes through the peripheral component interconnect bus to the first-in-first-out memory for data write-in until completion of a data transfer from the system memory through the host bus to the first-in-first-out memory for data read-out, thereby improving the throughput of the peripheral component interconnect bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.