On- the-fly partitionable computer bus for enhanced operation with varying bus clock frequencies
US5958033A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1997 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Aug 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for controlling a computer bus having first and second bus slots and operable with a bus controller at first and second data transfer rates. When the computer bus is operating at the first data transfer rate, the bus is partitioned so that the address/data pins of the bus controller are coupled to the address/data pins of both of the first and second bus slots, and the control pins of the bus controller are coupled only to the control pins of the second bus slot. When the computer bus is operating at the second data transfer rate, the bus is partitioned so that the address/data pins of the bus controller are coupled only to the address/data pins of the first bus slot, and the control pins of the bus controller are coupled only to the control pins of the first bus slot. The second data transfer rate may be faster than the first data transfer rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.