Method for precise architectural update in an out-of-order processor
US5958047A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1997 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Jun 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.