Host microprocessor with apparatus for temporarily holding target processor state
US5958061A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 1996 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Jul 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for use in a processing system having a host processor capable of executing a first instruction set to assist in running instructions of a different instruction set which is translated to the first instruction set by the host processor including circuitry for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor, circuitry for permanently storing memory stores temporarily stored when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor, and circuitry for eliminating memory stores temporarily stored when a determination is made that a sequence of translated instructions will generate an exception or error on the host processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.