Multiple node dual level error recovery system and method
US5958064A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1997 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Oct 23, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An error recovery method for use in an information communication system which comprises a plurality of nodes connected by links. Information is transferred between the nodes in frames of predefined types, including at least a first frame type used to transfer data and a second frame type used for error recovery. Each node has at least a first and a second mode of operation. In the first mode frames of both first and second types are accepted. In the second mode frames of the first type are discarded and only frames of the second type are accepted. A master node which controls error recovery is selected from amongst those nodes which can initiate transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.