Method and apparatus for reducing the bias current in a reference voltage circuit
US5959471A · kind A · utility
9Cited by
4References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 25, 1997 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Sep 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/462
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method for reducing the current consumption of a reference voltage circuit while a synchronous DRAM is in standby power-down mode is provided. The reference voltage is stored on a capacitor within the DRAM circuit. The reference voltage circuit is selectively disconnected from, and reconnected to the Vref-node at predetermined time intervals during a power down mode, in order to ensure leakage compensation. When the power down mode exceeds a predetermined time, the reference voltage circuit is disabled to further reduce the current consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.