Integrated circuit with speed detector
US5959487A · kind A · utility
20Cited by
3References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 16, 1997 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | May 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit is designed with a reference circuit (200) for generating a reference signal. The reference signal determines a reference period. A delay circuit (208, 212, 216) responsive to the reference signal produces a delay signal. A control circuit (248, 254, 258, 260, 262) responsive to the delay signal produces a control signal. The delay circuit emulates the speed of an integrated circuit for the reference period. Control signals from the control circuit compensate the integrated circuit performance for measured circuit speed variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.