Parallel-to-serial converter
US5959559A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 1997 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Dec 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A parallel-to-serial converter based on the principle of current evaluation that, in addition having signal paths, has a reference path with intentionally generated, poorer running time properties than all signal paths, and a conversion and a deactivation of a current source in an input hold element already occurring as soon as the reference path supplies a ready message. The advantages of this converter are particularly high signal processing speed and low dissipated power, but also low line crosstalk and small chip area. A further critical advantage is that the converter is adaptive in view of technology parameters, temperature and supply voltage, i.e. these quantities have nearly no influence on the functionability of the parallel-to-serial converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.