MPEG-2 transport stream decoder having decoupled hardware architecture
US5959659A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 1995 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Nov 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/426
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An MPEG-2 decoder having a decoupled architecture that allows the rapid acquisition of a program within an MPEG-2 transport stream. A digital signal processor (102) is provided to demultiplex a MPEG-2 transport stream provided on a line (110) into its constituent audio, video, and private data elementary streams. The digital signal processor is capable of performing a limited interpretation of program specific information in the transport stream data, prior to presentation of the program specific information to a host microprocessor (106). In particular, the digital signal processor can demultiplex and interpret back-to-back program association tables and program map tables carried in the transport stream. In the absence of a user selected program, the digital signal processor selects a default program to demultiplex and display to the user. The host microprocessor runs an operating system of the decoder, generates a user interface, and allows the user to select from the programs within the transport stream. Hardware framing logic (114) is also provided to generate and provide to the digital signal processor synchronizing bytes that correspond to the start of each transport packet …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.