Ferroelectric memory cell with shunted ferroelectric capacitor and method of making same
US5959878A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 15, 1997 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Sep 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory includes a transistor having a source/drain, a capacitor having a first electrode and a second electrode, and a plate line connected to the second electrode. The first electrode is connected to the source/drain of the transistor to create a node that is isolated when the transistor is off. A shunt system directly electrically connects the isolated node and the second electrode of said capacitor at a predetermined time to essentially equalize the voltages on the first and second electrodes of said capacitor during the predetermined time. In different embodiments the shunt is a Schottky diode, a resistor, and a pair of back-to-back diodes and a transistor. In the embodiment in which the shunt is a transistor, the shunt line connected to the shunt transistor gate is boosted, there is a shunt transistor connecting each isolated node in a portion of the memory, to the adjacent isolated node, and every eight to thirty-two isolated nodes, another shunt transistor connects the chain of isolated nodes to the plate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.