Column redundancy in semiconductor memories
US5959903A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 1997 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Jul 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention describes a column redundancy method and apparatus in a DRAM that minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required in repairing faulty columns. The invention discloses a DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for energizing appropriate memory columns in response to the decoder memory addresses received at an input thereof; redundant column drivers; and switch means for steering the decoded memory address onto one of either normal or redundant column driver paths. The invention further illustrates a fusing system which minimizes the capacitance of redundant select lines, thereby removing unnecessary delay in the redundant column path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.