Digital computer having a system for sequentially refreshing an expandable dynamic RAM memory circuit
US5959923A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 1993 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | May 7, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital computer which includes a memory refresh system for controlling the generation and sequencing of refresh signals to a memory subsystem comprised of at least one memory unit having a plurality of slots each capable of receiving a dynamic random access memory bank therein. The memory refresh system includes means for generating refresh signals and at least one independent refresh sequence controller for efficiently controlling the sequence in which the memory banks associated with a particular refresh sequence controller receive refresh signals. Each refresh sequence controller controls a combination of multi-stage shift registers for issuing refresh signals to memory banks installed on the corresponding memory unit and multi-stage shift registers for providing wait cycles during which refresh signals are being generated by other independent refresh sequence controllers. The order of refresh signals generated by each refresh sequence controller varies depending on the configuration of the memory subsystem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.