Dual clocking scheme in a multi-port RAM
US5959937A · kind A · utility
3Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1998 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Feb 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-port memory chip is provided with a DRAM main memory and a SRAM cache memory coupled via a global bus. Two clock pins are arranged on the opposite sides of the chip to supply external clock signals. Input clock buffers are provided near pads associated with the clock pins to produce buffered clock signals. A clock generator arranged on the chip uses the buffered clock signals to generate an internal clock signal for synchronizing memory operations. Four local clock buffers distributed on the memory chip are supplied with the buffered clock signals to produce local clock signals for synchronizing data output from data pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.