Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region

US5960289A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Paul G. Y. Tsui · Austin, US
• Hsing-Huang Tseng · Austin, US
• Navakanta Bhat · Bengaluru, IN
• Ping Chen · Dananyu, CN

Key dates

• Filing date: Jun 22, 1998
• Grant date: Sep 28, 1999
• Expiry date: Jun 22, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0144

Abstract

A method for forming a dual gate oxide (DGO) structure begins by forming a first oxide layer (106) within active areas (110) and (112). A protection layer (108a) is then formed over the layer (106). A mask (114) is used to allow removal of the layers (106 and 108a) from the active area (110). A thermal oxidation process is then used to form a thin second oxide layer (118) within an active area (110). Conductive gate electrodes (120a and 120b) are then formed wherein the first oxide layer (106) and the protection layer (108c) are incorporated into the gate dielectric layer of an MOS transistor (122a). The transistor (122b) has a thinner gate oxide layer that excludes the protection layer (108c).