System and method for accessing data between a host bus and system memory buses in which each system memory bus has a data path which is twice the width of the data path for the host bus
US5960450A · kind A · utility
6Cited by
10References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 24, 1992 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Dec 24, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.