Processor based BIST for an embedded memory

US5961653A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Howard L. Kalter · Colchester, US
• John E. Barth, Jr. · Williston, US
• Jeffrey H. Dreibelbis · Williston, US
• Rex Kho · Holzkirchen, DE
• John Stuart Parenteau, Jr. · Enosburg Falls, US
• Donald L. Wheater · South Burlington, US
• Yotaro Mori · Yokohama, JP

Key dates

• Filing date: Feb 19, 1997
• Grant date: Oct 5, 1999
• Expiry date: Feb 19, 2017

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/32
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated chip having a DRAM embedded in logic is tested by an in-situ processor oriented BIST macro. The BIST is provided with two ROMS, one for storing test instructions and a second, which is scannable, that provides sequencing for the test instructions stored in the first ROM, as well as branching and looping capabilities. The BIST macro has, in addition, a redundancy allocation logic section for monitoring failures within the DRAM and for replacing failing word and/or data lines. By stacking the DRAM in 0.5 mb increments up to a 4.0 mb maximum or in 1.0 mb increments up to an 8 mb maximum, all of which are controlled and tested by the BIST macro, a customized chip design with a high level of granularity can be achieved and tailored to specific applications within a larger ASIC.