Chip level bias for buffers driving voltages greater than transistor tolerance
US5963057A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Aug 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An integrated circuit includes a core region and an input-output (I/O) region which has an I/O slot and a voltage supply slot. First and second voltage supply buses and a bias voltage bus extend along the I/O region through the I/O slot and the voltage supply slot. A bias voltage generator is fabricated in the voltage supply slot and is electrically coupled between the first and second voltage supply buses. The bias voltage generator has a bias voltage output which is electrically coupled to the bias voltage bus. A buffer is fabricated in the I/O slot for interfacing with the core region. The buffer includes a bias voltage input which is electrically coupled to the bias voltage bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.