Semiconductor memory device
US5963467A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Dec 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device having a plurality of memory cells in which each memory cell is formed of an address selection MOSFET and an information storing capacitor and the plate voltage consisting of an intermediate potential is supplied to the common electrode of the information storing capacitor, the memory access is enabled by indirectly detecting that the plate voltage has reached a predetermined potential near a intermediate potential with the voltage detecting circuit or timer circuit, inhibiting the selecting operation of the word lines or precharging of the pair of bit lines to the intermediate potential when the plate voltage is lower than the predetermined potential, and then canceling the above inhibit condition after the plate voltage has reached the predetermined potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.