Static semiconductor memory device having a variable power supply voltage applied to a memory cell depending on the state in use and method of testing the same
US5963490A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Jun 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In carrying out testing, the potential of the node N1 of the state change detect circuit attains high level. This allows the power supply voltage supply line to receive a voltage down-converted by the voltage-down converter from the power supply voltage supplied from the power supply. In the normal use, the potential of the node of the state change detecting circuit attains a low level and the power supply voltage supply line receives the power supply voltage from the power supply. Since the power supply voltage supply line is connected to load elements for a memory cell and a voltage applied to the load elements for the memory cell is smaller than that in the normal use, the difference in potential between two storage nodes of the memory cell can be reduced as compared with that in the normal use. Thus, a condition comparable to that of an SRAM placed in the low-temperature environment can be created.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.