Sense amplifier with zero power idle mode
US5963496A · kind A · utility
6Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1998 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Apr 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controller manner, in response to a control pulse. The control pulse is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps are utilized to read out in parallel fashion the N memory cells (bits) that constitute an accessed memory location. The sense amps are therefore active only of a period of time sufficient to read out a memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.