Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing
US5963502A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 1998 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Jul 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A voltage controlled delay circuit having the same structure, except for a loop, as a voltage controlled oscillator included in a PLL circuit which in turn generates an internal clock signal from an external clock signal is controlled by a control voltage from the PLL circuit, and the delay output of the voltage controlled delay circuit is selected by a selection circuit in accordance with the output signal of a vernier-adjusting counter in order to generate a read clock signal. Therefore, a vernier for optimizing data input timing in a controller can be realized which always has a constant delay amount regardless of a change in operating environment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.