Phase error cancellation method and apparatus for high performance data recovery
US5963606A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Jun 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase error cancellation apparatus captures data bits of a serialized data stream with reduced phase error by aligning a generated clock signal to the data stream. The phase error cancellation apparatus includes a data delay pipe, a clock generator, a clock delay pipe, and a data stream sampling element. The data delay pipe receives the data stream and delays the data bits by a first amount. The clock generator generates a clock signal that the clock delay pipe delays by a second amount. The data stream sampling element receives the delayed data bits and the delayed clock signal, and samples the delayed data bits using the delayed clock signal to recover the data bits from the data stream with reduced phase error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.