Pipelined pyramid processor for image processing systems
US5963675A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Apr 15, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/85
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pipelined parallel processor (PPP) integrated onto a single integrated circuit. The PPP includes a filtering unit, internal routing circuitry such as a crosspoint switch, an internal frame store controller, and one or more function circuits. The function circuits may be, for example, arithmetic units, lookup tables, timing compensators, adders/subtractors, statistics modules, image shifting circuitry, and other useful processing devices. The components of the PPP are interconnected with the crosspoint switch which routes data between the frame store controller, the filtering unit, function circuits, external input channels, and external output channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.