Fabrication method for semiconductor package substrate and semiconductor package
US5963796A · kind A · utility
11Cited by
17References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 20, 1998 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Feb 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fabrication method for a chip package includes the steps of forming a first substrate having embedded leads, forming a second substrate with embedded leads and a central aperture therethrough, and attaching the second substrate to the first substrate to form a substrate with a recess for receiving a chip. A chip may then be mounted within the central aperture of the second substrate, on the first substrate, and bond pads of the chip may be attached to leads exposed on one of the first and second substrates with a plurality of metal wires. A resin may be molded over the device to protect the metal wires, the chip, and the leads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.