Mechanism for data strobe pre-driving during master changeover on a parallel bus
US5964856A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1997 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Sep 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a microprocessor system having a bus clock running at a bus clock rate, a method for reducing an idle interval between a first data transfer and a second data transfer, the method comprising the steps of: PA1 providing a first strobe signal and a second strobe signal for synchronizing said first and second data transfers with the bus clock; PA1 a pre-driving the first strobe signal before the first data transfer, the first strobe signal running at the bus clock rate during the first data transfer; and PA1 pre-driving one of the first and second strobe signals before the second data transfer, said one of the first and second strobe signals running at the bus clock rate during the second data transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.