Elastic self-timed interface for data flow elements embodied as selective bypass of stages in an asynchronous microprocessor pipeline
US5964866A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1996 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Oct 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a processor having a data flow unit for processing data in a plurality of steps. In one version, the data flow unit includes a plurality of consecutive stages which include logic for performing steps of the data processing, the stages being coupled together by a data path, at least one stage being coupled to a transceiver which causes data to be provided to the stage for processing or to bypass the stage unprocessed in response to a stage enable signal; a synchronizer which receives processed data from the stages and causes the processed data to be provided to external logic in synchronization with a clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.