Circuit interface synchronization using slave variable delay loop
US5964880A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1997 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Dec 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is provided for synchronizing clock signals. The method includes receiving a first reference clock signal, generating a second clock signal, modifying the second clock signal to synchronize a first feedback input clock signal with the first reference clock signal, and modifying the second clock signal to synchronize a second feedback input clock signal with a second reference clock signal. The apparatus includes a phase aligning device having a first reference clock input adapted to receive a first reference clock signal, a first feedback input, and an output. A fixed delay device is coupled between the output of the phase aligning device and the first feedback input of the phase aligning device. A slave loop is coupled to the output of the phase aligning device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.