Semiconductor device and a method of manufacture
US5965939A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1997 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Apr 22, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.