Output circuit for integrated circuit devices
US5966031A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1997 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Aug 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output circuit for an integrated circuit device in which first and second power wirings are connected to a high-potential power terminal, third and fourth power wirings are connected to a low-potential power terminal, and a plurality of inverters are responsive, respectively, to a plurality of bit data signals, each being formed of P-channel and N-channel MOS transistors having drains thereof connected together, a junction of which forms an output terminal. First to fourth auxiliary transistors are provided for each of the inverters, which are connected, respectively, between the first power wiring and the source of the P-channel MOS transistor, between the second power wiring and the source of the P-channel MOS transistor, between the third power wiring and the source of the N-channel MOS transistor, and between the fourth power wiring and the source of the N-channel MOS transistor. First and second circuits are provided for each inverter and operable in response to one of the bit signals corresponding to each inverter to control the transistors ON and OFF states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.