Optimized FIFO memory
US5966142A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 19, 1997 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Sep 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes an XY address for rendering the graphics primitives. A graphics processor, which includes a bypass logic circuit, enables the graphics processor to temporarily store display list commands in an internal storage device while previously fetched display list data is being processed. The bypass logic circuit allows the graphics processor to bypass the internal storage device and write fetched command directly to an execution unit in the graphics processor. By having the bypass capabilities, the graphics processor is able to optimize the internal storing of commands in the display list in the internal storage unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.