Method for verifying protocol conformance of an electrical interface
US5966306A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1997 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Jul 7, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and technique for verifying bus protocol in the design of integrated circuits. A correctness evaluator receives simulation results from a monitor file and prediction information generated from protocol templates. The correctness evaluator operates according to a "clean bus" theory that an error includes those events not specified by the circuit specification, including spurious transitions. Protocol templates define the elements within the circuit, and are provided to a prediction generator which creates a prediction file. The correctness evaluator compares a simulation monitor file to the prediction file, and outputs a pass or fail result. The present invention offers a flexible method to separate protocol-defined timing constraints from implementation-dependent timing constraints. The present invention allows input from a test program to tailor bus signal change predictions and verify that the test program performs as it is programmed to perform.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.