Structure and method for instruction boundary machine state restoration
US5966530A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 1997 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Jun 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring state at any instruction boundary; (3) tracking instruction status; (4) checkpointing instructions; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state. In one embodiment of the invention, a method of restoring machine state in a processor at any instruction boundary is disclosed. For any instruction which may modify control registers, the processor is either synchronized prior to execution or an instruction checkpoint is stored to preserve state; and for any instruction that creates a program counter discontinuity an instruction checkpoint is stored. Instruction execution status is monitored to detect a fault condition and if a fault occurs, the instruction identifier is saved according to predetermined rules and used as an endpoint to ba…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.