Signal processor and method for Fourier Transformation
US5968112A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1997 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Sep 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Parallel signal processor (10) (FIG. 2) performs a Fourier Transformation of an input signal; The transformation coefficients are converted once to logarithmic form and stored in a cache memory. The input data is converted serially to logarithmic form, and fed to all processing units in parallel. The processing units compute their respective products as additions in the logarithmic domain. Then, the products are converted back to the normal domain. The products with the correct sign are summed by an accumulator of the respective processing element. After the last signal data point has run through the processing elements and the last products are added to their respective sums, all complex output signal data points are complete simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.