System for selectively connecting CPU bus to DMAC bus when accessing device connected to DMAC bus is granted and DMA controller has right to access DMAC bus
US5968145A · kind A · utility
4Cited by
5References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 5, 1997 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Jun 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing unit capable of solving a conventional problem in that a CPU cannot acquire the right of using a bus as long as a DMAC (Direct Memory Access Controller) has that right, and hence the operating ratio of the CPU reduces. A CPU bus is kept disconnected from the DMAC bus as long as the CPU disables the access request to a memory connected to the DMAC bus, and is connected to a DMAC bus in response to the access request unless the DMAC has the right of using a DMAC bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.