Split-gate memory device and method for accessing the same
US5969383A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1997 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Jun 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
An EEPROM device includes a split-gate FET (10) having a source (36), a drain (22), a select gate (16) adjacent the drain (22), and a control gate (32) adjacent the source (36). When programming the split-gate FET (10), electrons are accelerated in a portion of a channel region (38) between the select gate (16) and the control gate (32), and then injected into a nitride layer (24) of an ONO stack (25) underlying the control gate (32). The split-gate FET (10) is erased by injecting holes from the channel region (38) into the charge nitride layer (24). When reading data from the split-gate FET (10), a reading voltage is applied to the drain (22) adjacent the select gate (16). Data is then read from the split-gate FET (10) by sensing a current flowing in a bit line coupled to the drain (22).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.