Clock driver circuit and semiconductor integrated circuit device incorporating the clock driver circuit
US5969544A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1997 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Jun 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
Abstract
A plurality of macro cell layout regions 9 in cell regions 2 on a semiconductor substrate 1 are divided into three portions in a second direction. Each of the divided portions is provided with basic circuits 14a through 14c. In each basic circuit, a first common line 16 is connected to an output node of a clock input driver 11 via a clock output line 17. A plurality of predrivers 15(1) through 15(n) have their input nodes IN connected to the first common line 16 and have their output nodes OUT connected to a second common line 18. A plurality of main drivers 19(1) through 19mhave their input nodes IN connected to the second common line 18 and have their output nodes OUT connected to a third common line 20. The third common line is connected to a plurality of clock signal supply lines 21(1) through 21(s) commonly provided to the basic circuits 14a through 14c. The clock signal supply lines 21(1) through 21(s) are connected to clock input nodes of internal circuits 22 each requiring a clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.