Dual loop delay-locked loop
US5969552A · kind A · utility
32Cited by
4References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1998 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Jan 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device and method for synchronizing a local clock to a reference clock. The device uses a frequency acquisition loop and a phase acquisition loop. The frequency acquisition loop delays the reference clock to produce an intermediate clock which falls within the operating range of the phase acquisition loop. The phase acquisition loop then delays the intermediate clock to produce a local clock synchronized to the reference clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.