Division circuit and the division method thereof
US5969976A · kind A · utility
Assignees
Inventors
- Shumpei Kawasaki
- Eiji Sakakibara
- Kaoru Fukada
- Takanaga Yamazaki
- Yasushi Akao
- Shiro Baba
- Toshimasa Kihara
- Keiichi Kurakazu
- Takashi Tsukamoto
- Shigeki Masumura
- Yasuhiro Tawara
- Yugo Kashiwagi
- Shuya Fujita
- Katsuhiko Ishida
- Noriko Sawa
- Yoichi Asano
- Hideaki Chaki
- Tadahiko Sugawara
- Masahiro Kainaga
- Kouki Noguchi
- Mitsuru Watabe
Key dates
| Filing date | Oct 10, 1997 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Oct 10, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5352
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A division method and circuit performs a division for signed data by adding or subtracting a divisor to or from the dividend or the partial remainder from the division, according to the sign of the divisor or the dividend and the partial remainder to acquire a new partial remainder. The division is repeated a predetermined number of times in which a quotient bit is acquired according to the sign of the acquired partial remainder or the divisor. The dividend is corrected by subtracting 1, which is the significance of an LSB of the corresponding dividend, from the dividend when the sign of the dividend is negative, and the corrected dividend is used for the division processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.