Dynamic RAM provided with a defect relief circuit
US5970001A · kind A · utility
21Cited by
1References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1998 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Mar 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An X address buffer for generating an internal address signal by capturing an X address signal input from an address terminal is brought into an operating state before an external control clock is input. A redundancy address comparator for detecting a match/mismatch signal by comparing the generated internal address signal with a stored X-system defective address is used as a static circuit. Thereby, the redundancy address comparator starting operation is accelerated and as a result, acceleration of the reading operation is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.