Arithmetic apparatus for use in Viterbi decoding
US5970097A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1997 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Oct 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6569
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An arithmetic apparatus comprising a memory 1 for storing path select signals, a barrel shifter 3 for shifting data read from the memory, a shift register 4 for receiving a bit shifted to a MSB by the barrel shifter and means 5 for generating the number of shifts which are performed by the barrel shifter by converting data positioned at a specific bit position in the shift register, wherein path select signals at the same time are divided into a plurality of groups, and then stored in the memory, and the arithmetic apparatus includes address generating means 10 for outputting the address, and address conversion means 7 for generating the address of the group which must be read by combining the address and a value of a specific bit position in the shift register with each other. Thus, tracing back in Viterbi decoding can be performed with a short bit width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.