CMOS output buffer having load independent slewing
US5973512A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 1997 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Dec 2, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
n A buffer having an output slew rate which is relatively insensitive to loading and supply voltage. The output buffer includes an output node, a first half-circuit and a second half-circuit. The first half-circuit is for slewing the output node from a first voltage to a second voltage. The first half-circuit includes a first output transistor connected between the output node and a second voltage reference node, a first switching device connected from a gate of the first output transistor to the second voltage reference node, a second switching device connected from the gate of the output transistor to a first node, a first current source connected from a first voltage reference node to the first node, and a first capacitor connected from the output node to the first node. The second half-circuit is for slewing the output node from the second voltage to the first voltage. The second half-circuit includes a second output transistor connected between the output node and the first voltage reference node, a third switching device connected from the gate of the second output transistor to the first voltage reference node, a fourth switching device connected from the gate of the second …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.