System and method for performing motion estimation with reduced memory loading latency
US5973742A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 1997 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Aug 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/51
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system and method for estimating motion vectors between frames of a video sequence which operates with reduced memory loading latency according to the present embodiment. The motion estimation system includes a motion port pixel processing array according to the present embodiment. The processing array includes a reference block memory array for storing a reference block and a candidate block memory array for storing a candidate block. According to the present embodiment, each of the reference block memory array and candidate block memory array are configured with dual ports to a reference block memory and a search window memory. Each of the reference block memory array and candidate block memory array are further configured to allow dual port loading during the entire initialization sequence, when one or more of either a reference block or candidate block is being loaded into the respective memory array. During initialization or loading, memory elements for each of the reference block and candidate block are loaded in parallel according to the present embodiment. This reduces the clock latency of the initial loading of the memory array as well as subsequent loadings of a new can…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.