Method for operating a SRAM MOS transistor memory cell

US5973965A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Jorg Berthold · Munich, DE
• Jürgen Dresel · Lambach, DE

Key dates

• Filing date: Jun 22, 1998
• Grant date: Oct 26, 1999
• Expiry date: Jun 22, 2018

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/409
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In a method for operating an SRAM MOS transistor memory cell, the memory cell comprises a 6-transistor memory cell composed of two inverters with feedback, each of which is connected to a bit line via a selection transistor which is driven by a word line. Both selection transistors are switched on when writing information to the memory cell. Only the first selection transistor is switched on, the other selection transistor remaining switched off, when reading the contents of the cell. In this way, the charge on only one bit line is changed when reading.