Synchronizing circuit
US5974102A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1997 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Sep 15, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In case microcontroller and digital signal processing blocks are used together in one chip, there has been a problem in which the synchronization of the clocks are not consistent with each other when sending a signal from one block to another. In addition, when a reference clock is activated during a change of input signal, an incomplete interval has occurred. Accordingly, in order to solve the above mentioned problem, the present invention discloses a synchronizing circuit which uses a latch circuit("RS") consisted of NAND gates to synchronize an asynchronous input data and a reference clock, thereby solving the problem in which an incomplete interval occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.