Address decoder with memory wait state circuit
US5974402A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1993 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Dec 9, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG07B2017/00395
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An electronic postage meter control system having a printer for printing mixed graphic and alphanumeric information. The control system includes a programmable microprocessor in bus communication with the printer for controlling the printer and with a plurality of memory units for accounting for postage printed by the printer. The memory units include at least a first memory unit having a write access time shorter than the write access time of a second one of said memory unit, a program memory in bus communication with the programmable microprocessor having an operating program stored therein. The programmable microprocessor is able to access the operating program, an integrated circuit, the program memory, and said first and second units. The integrated circuit has an address decoding module for generating one of a plurality control signals in a unique combination in response to a respective request by the programmable microprocessor. Respective ones of the control signals are the memory write enable signals for write enabling the first or second units where write enable signals are directed to the respective memory unit. The control system further maintains the respective write e…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.