Enabling mirror, nonmirror and partial mirror cache modes in a dual cache system
US5974506A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1996 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Jun 28, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory system is enabled into one of a plurality of cache modes in a cache memory system in a computer. The cache memory system has a first controller and two cache memories, the cache memories are partitioned into quadrants with two quadrants in each cache memory. A cache mode detector in the first controller detects a mirror cache mode set for the cache memory system. An address enabler in the first controller enables access to first pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode. A second controller follows the cache mode set by the cache mode detector and has an address enabler. The address enabler in the second controller enables access to both quadrants in one cache memory in a non-mirror cache mode, and enables the access to a second pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode by said cache mode detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.