Machine for processing interrupted out-of-order instructions
US5974522A · kind A · utility
30Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1993 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Mar 9, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor having multiple functional units. The processor is capable of executing multiple instructions concurrently. An instruction issuing unit is connected to a mechanism for handling an interrupt of the processor. The interrupt handler has an instruction window (IW), which includes a vector element number (VEN) field that indicates the uncompleted elements to be executed. Upon termination of the interrupt, normal processing of the instruction issuing unit continues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.