Integrated PCI buffer controller and XOR function circuit
US5974530A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 1997 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Oct 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated buffer controller and data function circuit includes a data function circuit that is controlled by addresses supplied to the circuit. The integrated buffer controller and data function circuit has a bus interface that is used to connect the circuit to a bus on which one or more host adapters are connected so that both the host adapters and a host computer can transfer data to and from the circuit, and supply addresses to control operation of this data function circuit. A data channel in the integrated buffer controller and data function circuit connects the bus interface to a buffer memory controller. The buffer memory controller has a buffer memory port that includes a data port, a memory address port, and a memory control port. A buffer memory is connected to the buffer memory port. A data function circuit in the buffer memory controller is coupled to a data function enable output line. The data function circuit is selectively connected to the data port by a signal on the data function enable output line. In one embodiment, the data channel is a slave data channel. The integrated buffer controller and data function circuit also includes a master data channel connect…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.