Fabrication process of semiconductor package and semiconductor package
US5976912A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1996 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Sep 18, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.