High density gate array cell architecture with sharing of well taps between cells

US5977574A · kind A · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Jonathan Schmitt · Eden Prairie, US
• Timothy V. Statz · Minneapolis, US

Key dates

• Filing date: Mar 28, 1997
• Grant date: Nov 2, 1999
• Expiry date: Mar 28, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/907

Abstract

An arrangement and method for making a gate array architecture locates the well taps at the outer corners of each gate cell. The power buses are also located at the outside of the gate cell as well, enabling sharing of the well taps and the power buses. The location of the well taps at the outside corners of the standard cell reduces the number of transistors in a single repeatable cell from eight transistors to four transistors.